Method of cyclically converting an analog signal to a mullti-bit digital signal and converter for performing the method

ABSTRACT

Method and arrangement for cyclically AD converting an analog signal with a sampler capacitance and an integrator capacitance, comprising the steps of generating a difference signal multiplied by the ratio of said capacitances from the analog signal and a reference signal, deriving a digital bit from said difference signal, doubling the difference signal multiplied by said ratio, shifting said doubled signal by the reference signal multiplied by said ratio and using the shifted signal as difference signal multiplied by said ratio for the next cycle.

The present invention relates to a method for cyclically converting ananalog input signal (V_(in)) to a digital output signal with a samplercapacitance (C₁) and an integrator capacitance (C₂).

Such AD-conversion is e.g. known from the U.S. Pat. No. 5,107,266.Cyclic AD-conversion has become popular because its integration on asemiconductor chip requires only a small chip area while with presentday technology the conversion can be performed with relatively highspeed. However, since operational amplifiers, integrated capacitors andMOST-switches are used, problems with such cyclic AD converters arecapacitor mismatch, input offset voltage of the operational amplifierand the comparator, clock feed-through, channel charge injection andleakage currents of the switches. Input offset voltage of theoperational amplifier and the comparator may be cancelled by so calledauto-zero techniques that requires only a small amount of passivecomponents. Channel charge injection and leakage currents may be solvedby using fully differential structures by which all the excess chargesbecome common mode signals which are cancelled at the output. Clockfeed-through may be cancelled by tuning the clock pulses with a smalldifference from pulse to pulse. A remaining problem is the disturbingeffect of capacitor mismatch that occurs on the digital output signal,because of the fact that the sampler capacitor and the integratorcapacitor are not sufficiently equal and because parasitic capacitanceshave different influence on these two capacitances.

The above-mentioned US patent has as its main intention to cancel theoffset voltage of the operational amplifier but does not solve thecapacitor mismatch. In contradistinction therewith it is an object ofthe present invention to substantially minimize the effect of capacitormismatch in a cyclic AD-converter. The method according to the inventionis therefore characterized by comprising the steps of generating adifference signal by multiplying the difference of the analog signal(V_(i)) and a reference signal (V_(r)) by the ratio (C₁/C₂) of saidcapacitances, deriving at least one digital bit (D) from said differencesignal, substantially doubling the difference signal, shifting saiddoubled difference signal by the reference signal multiplied by saidratio and using the shifted signal as difference signal multiplied bysaid ratio for a next cycle.

It has to be observed that the above-mentioned steps need notnecessarily be executed in the given succession. For instance it is alsopossible to execute the shifting operation prior to the multiplyingoperation.

A preferred embodiment of the method according to the invention is amethod whereby the digital output signal is a multi-bit digital wordgenerated by means of an operational amplifier (A) having anopamp-output connected to a comparator (Q), the sampler capacitor (C₁),the integrator capacitor (C₂) and switch means (S₀ . . . S₈) arrangedand controlled to perform the conversion, characterized by:

generating the difference signal during a first phase-group of one ormore clock-phases at the opamp-output (O),

deriving the at least one digital bit (D) during a second phase-group ofone or more clock-phases for constituting the digital word anddelivering at said opamp-output (O) said difference signal multiplied bysaid capacitance ratio,

substantially doubling the difference signal by generating during athird phase-group of one or more clock-phases at the opamp-output (O) adoubled difference signal which is substantially twice said analogdifference signal multiplied by said capacitance-ratio,

shifting said doubled difference signal by generating during a fourthphase-group of one or more clock-phases at the opamp-output a shiftedanalog signal which is the opamp-output signal delivered by the previousphase-group shifted by a bit-dependent reference signal multiplied bysaid capacitance ratio, and

using said shifted signal as difference signal for the secondphase-group of the next cycle.

It has to be observed that the above-mentioned phase-groups need notnecessarily be executed in the given succession. For instance it is alsopossible to execute the shifting operation of the fourth phase-groupprior to the multiplying operation of the third group.

In practice capacitance ratios will differ from their ideal or nominalvalues due to for instances tolerances during the manufacturing of thecapacitors. The present invention is based on the insight that it isallowable to have the signal delivered by each phase-group to the nextphase-group be “corrupted” by the capacitance ratio, provided that eachof said analog signals is proportional to said capacitance ratio. Thisin contrast to the above-mentioned prior art where corrupted analogsignals are added to uncorrupted analog signals, which results in a bitgeneration that may be seriously corrupted by the capacitance ratiobeing unequal to one.

In many applications one bit of the digital output signal is generatedin one cycle of the cyclic AD-converter. Then, during the secondphase-group, the bit value is determined by the polarity of the analogdifference signal e.g. the bit is “high” when the analog differencesignal is positive and the bit is “low” when the analog differencesignal is negative. This decision criterion is not affected by the factthat the difference signal is multiplied by the capacitance ratio.However, if it is desired to compare the difference signal with a fixedreference value unequal to zero it is of importance to remove thecapacitance ratio from the output signal of the opamp before this signalis applied to the comparator and the method according to the presentinvention may then be characterized by transferring during the secondphase-group the charge of the integrator capacitor into the samplercapacitor, generating said at least one bit for constituting the digitalword from the voltage across the sampler capacitor and subsequentlytransferring the charge of the sampler capacitor back into theintegrator capacitor.

The multiplication by the factor two during the third phase-group may bedone by copying, with the aid of the opamp, the voltage across theintegrator capacitor to the sampler capacitor and subsequently, againwith the aid of the opamp, transferring the charge of the samplercapacitor to the integrator capacitor. In this way the voltage acrossthe integrator capacitor and also the opamp-output voltage is onlyexactly doubled if the capacitances of the two capacitors are exactlyequal. Therefore, when the capacitances are not sufficiently equal themultiplication factor is corrupted which results in a corruptedbit-generation during the second phase group of the next cycle.

In case the difference between these capacitances is not sufficientlysmall their matching may be improved if the method according to thepresent invention is characterized by an iterative calibration processcomprising the steps of charging the sampler capacitor with acalibration voltage, of transferring the charge of the sampler capacitorto the integrator capacitor, of comparing the voltage across theintegrator capacitor with said calibration voltage and of addingtrimming capacitance to the sampler capacitance if the result of saidcomparison is higher than 1 and by adding trimming capacitance to theintegrator capacitance when the result of the comparison is lowerthan 1. It may be noted that the use of trimming capacitors to improvethe equality of capacitances in a cyclic AD-converter is per se knownfrom U.S. Pat. No. 5,027,116.

An alternative method to make the multiplication factor more exactlyequal to 2 is characterized by the third phase-group comprising thesteps of storing the opamp-output voltage in first and second storagecapacitors, of connecting the first and second storage capacitors inseries with the input of the opamp and connecting the integratorcapacitor to the output of the opamp whereby the voltages of the firstand second storage capacitors are added in the integrator capacitor, andof subsequently connecting the integrator capacitor between theinverting input and the output of the opamp. One of the storagecapacitors may be connected in one of the input-leads of the operationalamplifier and the other storage capacitor may be connected in the otherinput lead. Alternatively both storage capacitors may beseries-connected in one of the input leads, preferably the lead to theinverting input of the opamp. It is noted that, whereas the samplercapacitor and the integrator capacitor are for instance relatively largepolysilicon or metal capacitors of e.g. 1 pF, the storage capacitor(s)may be small MOS (gate-oxide) capacitors of e.g. 0.1 pF that do use upsubstantially less chip area. Conveniently the sampler capacitance maybe used as one of the storage capacitors because the sampler capacitorwould otherwise be idle during this phase group and it saves an extracapacitor and some switches.

The invention also covers a cyclic switched capacitor AD-converterspecifically intended for carrying out a method according to one or moreof the accompanying claims.

The invention will be described with reference to the accompanyingfigures. Herein shows:

FIG. 1 a schematic diagram of a cyclic AD converter according to theinvention,

FIGS. 2 a and 2 b the topology of the clock phases of the AD converterof FIG. 1,

FIG. 3 the topology of the clock phases of a modification of the ADconverter of FIG. 1,

FIG. 4 the topology of the clock phases of a process for trimming thecapacitors of a cyclic AD converter according to the invention,

FIG. 5 a second modification of the cyclic AD converter according to theinvention,

FIG. 6 the topology of the clock phases of the modification of FIG. 5,

FIG. 7 a fully differential implementation of the cyclic AD converter ofFIG. 1 and

FIG. 8 a third modification of the cyclic AD converter according to theinvention.

The cyclic switched capacitor AD-converter of FIG. 1 comprises an inputterminal I for an analog input signal V_(i), an input terminal R for areference voltage V_(r) that lies half way in the range between theminimum and the maximum value of V_(i), a sampler capacitor C₁, anintegrator capacitor C₂, an operational amplifier (opamp) A with anopamp-output terminal O and a comparator Q having its input connected tothe output of the opamp. The converter further comprises a plurality ofswitches S₀ . . . S₈. The switch S₀ bridges the capacitor 2. Theswitches S₁ and S₂ respectively connect the input terminals I and R tothe left hand plate of capacitor C₁, the switches S₃ and S₈ respectivelyconnect the left hand plate of C₁ to ground and to the opamp-output O,the switches S₄ and S₅ respectively connect the right hand plate of C₁to ground and to the inverting input of the opamp A and the switches S₆and S₇ respectively connect the right hand plate of the integratorcapacitor C₂ to ground and to the opamp-output O. The inverting input ofthe opamp is connected to the left hand plate of the capacitor C₂ andthe non-inverting input of the opamp is connected to ground. Theconverter further contains a clock-pulse controlled pulse generator P₁with a clock-pulse input CL, a start pulse input S_(t) and ninepulse-outputs for controlling the open- and close-phases of the nineswitches S₀ . . . S₈.

The operation of the converter of FIG. 1 will be explained withreference to FIGS. 2 _(a)-2 _(b) which shows the topology of theconverter during the various clock phases. The clock phases indicated(1) and (2) together form the first phase-group for generating thedifference signal, clock phase (3) alone constitutes the secondphase-group for generating the digital bit D, clock phases (4) and (5)form the third phase-group serving the multiplication of the differencesignal by the factor 2 and clock phases (6) and (7) (see FIG. 2 _(b))form the fourth phase-group for the bit-dependent shifting of themultiplied difference signal. The signal generated in clock-phase (7) isused as input signal for the next cycle that starts with clock phase(3). Therefore each cycle consists of the clock-phases (3) to (7); theclock-phases (1) and (2) fall outside the cycle and serve the generationof the difference signal for entering the first cycle. During theexecution of the first cycle the most significant bit of the digitaloutput is produced and during each further cycle each lesser significantbit. The digital word is available at the output of the converter inserial format and may be transformed into parallel digital words in aserial to parallel converter (not shown).

(1) During the first clock phase the switches S₀, S₁ and S₄ are closedand the other switches are open. The input voltage V; charges thesampler capacitor C₁ through the switches S₁, S₄ and the voltage acrossthe integrator capacitor 2 is reset to zero through the switch S₀.(2) During the second phase the switches S₂, S₅ and S₇ are closed andall other switches are open. The inverting input of the opamp is atvirtual ground due to the feedback through the integrator capacitor C₂.The reference voltage V_(r) is applied to the left hand plate of C₁thereby changing the charge of C₁ by (V_(i)−V_(r)).C₁. This change incharge is shifted into the capacitor C₂ thereby generating a voltage(V_(i)−V_(r)).C₁/C₂ across this capacitor and at the opamp-output O.(3) During the third phase the switches S₃, S₄ and S₇ are closed and allother switches are open. The charge of C₁ is zeroed through S₃ and S₄.The opamp-output is unaltered. Because this clock phase is the start ofeach cycle the opamp-output is referenced in FIG. 2 a by V_(n).C₁/C₂ inwhich the subscript n denotes the number of the cycle actually executed.Therefore during the first cycle the opamp-output voltage of the thirdphase is Vo=V₁.C₁/C₂ with V₁=(V_(i)−V_(r)). This signal is applied tothe comparator Q to generate the first bit D. If V₁ is in the lower halfof its range V_(i)−V_(r) is negative and D=low. If V₁ is in the upperhalf of its range V_(i)−V_(r) is positive and D=high.(4) During the fourth phase the switches S₄, S₇ and S₈ are closed andall other switches are open. The output voltage Vo remains unchangedVo=V.C₁/C₂ but the sampler capacitor C₁ is effectively connected acrossthe opamp-output and this capacitor gets the same voltage as thecapacitor C₂.(5) During the fifth phase the switches S₃, S₅ and S₇ are closed and allother switches are open. The capacitor C₁ is connected between groundand the virtual ground of the inverting input of the opamp. Thereforethis capacitor looses its charge and this charge is transferred to theintegrating capacitor C₂. Consequently the voltage across this capacitorand also the opamp-output voltage Vo is substantially doubled what isexpressed by Vo=2V.C₁/C₂. The factor 2 is underscored to indicate thatthis factor is not independent from the capacitance ratio C₁/C₂. This isdue to the fact that the voltage Vn.C₁/C₂, impressed on C₁ during thefourth phase, results in a charge Vn.C² ₁/C₂ in this capacitor andduring the fifth phase this charge is added to the charge Vn.C₁ in C₂ sothat in the end a voltage V_(n).(1+C₁/C₂).C₁/C₂ results across thecapacitor C₂ and at the output of the opamp. As explained in theintroduction the factor C₁/C₂ does not affect the generation of the nextbit, but the term C₁/C₂ in the multiplication factor does have adverseeffect on this generation. In practice this error is relatively small,however this error is unacceptably high when the digital word to beproduced has 10 bits or more. In connection with FIGS. 3 to 5 methodsand arrangements to reduce or to avoid the error in the multiplicationfactor will be disclosed.(6) and (7) During the sixth and seventh clock phases the switchesclosed depend from the value of the bit D produced during the thirdphase. When D is low the switches S₂, S₄ and S₇ are closed and all otherswitches are open. The voltage across the capacitor C₂ remains unalteredand the sampler capacitor C₁ is charged by the reference voltage V_(r).When the seventh phase starts the switches S₂ and S₄ open and theswitches S₃ and S₅ close. The charge of C₁ now shifts into C₂ wherebythe voltage across C₂ and the opamp-output voltage increase by Vr.C₁/C₂.It is important that this voltage shift is proportional to the capacitorratio C₁/C₂ with the result that the output voltageVo=(2V_(n)+V_(r)).C₁/C₂ remains proportional to this capacitor ratio.

When the bit D generated during the third clock-phase is high theswitches closed during the sixth phase are S₃, S₄ and S₇. In fact thevoltages across the two capacitors are unchanged with respect to thevoltages generated during the fifth phase but the sixth phase isnecessary to keep the sequence in synchronism with the sequence when Dis low. During the seventh phase the switches S₂, S₅ and S₇ are closedand all other switches are open. Now the capacitor C₁ is loaded by thecharge V_(r).C₁ and this charge is subtracted from the charge ofintegrator capacitor C₂. This results in the voltage(2V_(n)−V_(r)).C₁/C₂ across the capacitor C₂ and at the opamp-output.

Thereafter the sequence is repeated for the production of the next bit,starting with the third phase (3) whereby the analog voltageV_(n+1)=2V_(n)+V_(r) for D is low and V_(n+1)=2V_(n)−V_(r) for D ishigh.

When for some reason during the second phase group the bits have to beproduced by comparing the difference signal V_(n).C₁/C₂ with acomparison value that is unequal to zero, the factor C₁/C₂ will disturbthe production of the bit. This may be avoided by replacing the secondphase group consisting of phase (3) by the phase group with three clockphases (3 a), (3 b) and (3 c) shown in FIG. 3.

(3 a) During the phase (3 a) the switches S₃, S₄ and S₇ of FIG. 1 areclosed and all other switches are open, just as in the original phase(3). The difference is that in phase (3 a) the opamp-output signal isnot yet compared in the comparator Q. The capacitor C₁ is discharged andthe charge V_(n).C₁ in capacitor C₂ is preserved.(3 b) During this phase the switches S₅, S₆ and S₈ are closed and allother switches are open. The charge V_(n).C₁ of capacitor C₂ istransferred to C₁ with the result that the voltage across C₁ and alsothe opamp-output voltage Vo is equal to V_(n) i.e. this voltage is notcorrupted by the capacitance ratio C₁/C₂ and can therefore be comparedin comparator Q with any suitable reference voltage V_(c).(3 c) This phase, during which the switches S₃, S₅ and S₇ are closed andall other switches are open, serves to restore the situation of phase (3a). The charge of capacitor C₁ is retransferred to the capacitor C₂ andagain the output voltage of the opamp is V_(n).C₁/C₂.

With the method disclosed above with reference to FIGS. 1 to 3 thedependency of the bits on the capacitor mismatch is substantiallyreduced by about 75% with respect to the prior art, however theremaining mismatch dependency due to the corrupted multiplication factor2 may still be too high in practice. FIG. 4 discloses a method tofurther reduce the mismatch problems by means of a trimming process thatreduces the inequality between the sampler capacitor C₁ and theintegrator capacitor C₂. This trimming process may e.g. be executed atthe start of a conversion or with regular intervals during a conversion.

During a first phase (T₁) of the trimming process the switches S₀, S₂and S₄ of FIG. 1 are closed and all other switches are open. The samplercapacitor is charged by the reference voltage V_(r) and simultaneouslythe integrator capacitor C₂ is discharged. It may be noted that insteadof the reference voltage V_(r) any other suitable constant voltage maybe used for the trimming process.

During a second phase (T₂) the switches S₃, S₅ and S₇ of FIG. 1 areclosed and all other switches are open. Thereby the charge V_(r).C₁ ofcapacitor C₁ is transferred to the capacitor C₂, so that across thiscapacitor and at the opamp-output a voltage V_(r).C₁/C₂ occurs.

During a third phase (T₃) this opamp-output voltage is applied to thecomparator Q where this voltage is compared with the reference voltageV_(r). The comparator delivers a bit B that is high when theopamp-output voltage is higher than V_(r), i.e. if the capacitance of C₁is larger than that of C₂ and that is low when the capacitance of C₁ islower than that of C₂. The bit B is applied to a pulse generator P₃ thatgenerates pulses L₁, H₁, K₂ and K₃ for controlling correspondingswitches shown in FIG. 4 in the fourth phase (T₄) of the trimmingprocess.

In FIG. 4 the topography of this fourth phase shows the two capacitorsC₁ and C₂, two switches L₁ for connecting a trimmer capacitor C_(p1) inparallel with the capacitor C₁ and two switches H₁ that connect thetrimmer capacitor C_(p1) in parallel with the capacitor C₂. A switch K₂is provided for connecting a second trimmer capacitor C_(p1) in parallelwith the first trimmer capacitor C_(p1) and a switch K₃ serves theconnection of a third trimmer capacitor C_(p3) in parallel with thesecond trimmer capacitor C_(p1).

In operation, when the capacitance of C₁ is lower then the capacitanceof C₂, the bit B is low and this makes the pulse generator to close thetwo switches L₁. The trimmer capacitor C_(o) is connected in parallelwith the capacitor C₁ thereby making the capacitance ratio C₁/C₂ higher.A new trimming cycle starts and if the capacitance ratio C₁/C₂ is stilltoo low the pulse generator P₃ generates a pulse for the switch K₂ sothat the second trimmer capacitor is also connected in parallel with C₁.Again a new cycle starts and if the ratio C₁/C₂ is now higher than 1 nofurther pulse is delivered by the pulse generator P₃ and the trimmingprocess is halted. On the other hand, when the ratio is still lower than1 a pulse for the switch K₃ is generated and the trimming capacitorC_(p3) is connected in parallel with C₁, C_(p1) and C_(p1). If duringthe first cycle the ratio C₁/C₂ is higher than 1 the switches H₁ areclosed instead of the switches L₁ and the same procedure increases thecapacitance C₂.

In practice the trimming capacitors C_(o), C_(p1) and C_(p3) may havevalue of about 1% of the capacitance of C₁ and C₂. If necessary thetrimming range may be increased by increasing the number of trimmingcapacitors and the resolution of the trimming process may be increasedby decreasing the capacitance value of the trimming capacitors both ofcourse at the expense of more iterations in the calibration process.

Another method to reduce the influence of the capacitor mismatch on themultiplication factor in the cyclic AD converter of FIG. 1 is explainedwith reference to the FIGS. 5 and 6. The elements of FIG. 5 thatcorrespond to elements of the converter of FIG. 1 have been given thesame reference numerals. The cyclic AD converter of FIG. 5 additionallyhas five switches S₉ to S₁₃ and a storage capacitor C₃. The switches S₉and S₁₀ connect the left hand plate of integrator capacitor C₂respectively to the inverting input of the opamp and ground. The storagecapacitor C₃ has one plate grounded while the other plate is connectedthrough switches S₁₁ and S₁₂ to respectively the output and thenon-inverting input of the opamp. Moreover a switch S₁₃ is connectedbetween this non-inverting input and ground. A pulse generator P₂ hasoutputs for controlling each of the switches S₀ to S₁₃.

The first phase group with the clock phases (1) and (2), the secondphase group with the clock phases (3) or (3 a), 3(b), 3(c) and thefourth phase group with the clock phases (6) and (7) are identical tothose as described and shown earlier with reference to FIGS. 1, 2 a-2 band 3. Only the fourth phase group performing the multiplication by thefactor 2 is replaced by the clock phases (4 a), (5 a) and (5 b) shown inFIG. 6. The operation is as follows:

(4 a) During this clock phase the switches S₄, S₇, S₈, S₉, S₁₁ and S₁₃are closed and the other switches are open. The opamp-output voltageVo=V_(n).C₁/C₂ is unchanged and impressed upon the two capacitors C₁ andC₃.(5 a) During clock phase (5 a) the switches S₅, S₇, S₈, S₁₀ and S₁₂ areclosed and all other switches are open. The storage capacitor C₃ isconnected to the non-inverting input of the opamp and consequentlyraises all the voltages of the opamp by V_(n).C₁/C₂. Moreover thecapacitor C₁ that is now connected between the inverting input and theoutput of the opamp raises the output voltage of the opamp by anotherV_(n).C₁/C₂ so that the opamp-output voltage is now doubled to2.Vn.C₁/C₂. This voltage is impressed on the capacitor C₂. Themultiplication factor 2 that in the arrangement of FIG. 1 was corruptedby the capacitance ratio C₁/C₂ is uncorrupted in the arrangement of FIG.5.(5 b) During clock phase (5 b) the switches S₃, S₄, S₇, S₉ and S₁₃ areclosed and all other switches are open. The capacitor C₁ is dischargedand the capacitor C₂ with the multiplied voltage 2.Vn.C₁/C₂ is switchedback to its normal position between the inverting input and the outputof the opamp.

It may be noted that the storage capacitor C₃ may have a much smallercapacitance than the capacitors C₁ and C₂ because C₃ need not to delivercharge to another capacitor, but only has to raise the voltage of theopamp inputs. For the capacitor C₁ in FIG. 6 also a small storagecapacitor may be used but this would mean that more switches arerequired.

The arrangements shown and described above may be extended to a fullydifferential structure. An example thereof is shown in FIG. 7 that showsa differential structure of the arrangement of FIG. 1. The opamp A′ is adifferential amplifier with a two-terminal (differential) output. Thearrangement comprises two sampler capacitors C₁ and C′₁ and twointegrator capacitors C₂ and C′₂ while also each of the switches S₀ . .. S₈ has its differential counterpart S′₀ . . . S′₈. The common modevoltage Vc is usually about equal to half the supply voltage to have anoptimal voltage swing. The input consists of differential input signalsV_(ip) and V_(in) that are centered around V_(c) and also the referencesignal consists of differential reference signals V_(rp) and V_(rn) thatare centered around V_(c).

The arrangement of FIG. 5, with the storage capacitor C₃ connected tothe non-inverting input of the opamp, cannot be extended to a fullydifferential structure because then the non-inverting input of the opampis not available for the multiplication by two. This problem may besolved by modifying the arrangement of FIG. 5 so that the storagecapacitor C₃, instead of being connected to the non-inverting input ofthe opamp, is connected with proper polarity in series with thecapacitor C₁ between the opamp output and the inverting input of theopamp. This leaves the non-inverting input free for the differentialoperation. This modification of FIG. 5 is shown in FIG. 8 in whichcorresponding elements with those of FIG. 5 have the same referencenumerals.

The clock-phase topologies of this arrangement are identical to those ofthe arrangement of FIG. 5 except in that the clock-phase topology (5 a)shown in FIG. 6 is replaced by the clock-phase topology (5 c) shown inFIG. 8. The clock-phase topologies of FIG. 3 are not implemented in thearrangement of FIG. 8. Therefore the clock-phase topologies of FIG. 8are (1), (2), (3), (4 a), (5 c), (5 b), (6), (7) and the switches ofFIG. 8 that are closed during the clock-phases are:

(1) S₁, S₄, S₉ (S₁₄, S₁₆) (2) S₂, S₅, S₁₄, S₁₅, S₉ (3) S₃, S₄, S₉ (S₁₄,S₁₆) (4a) S₄, S₈, S₁₆, S₁₇, S₉ (5c) S₁₅, S₅, S₈, S₁₀ (5b) S₃, S₄, S₉(S₁₄, S₁₆) D low D high (6) S₂, S₄, S₉ (S₁₄, S₁₆) S₃, S₄, S₉ (S₁₄, S₁₆)(7) S₃, S₅, S₁₄, S₁₅, S₉ S₂, S₅, S₁₄, S₁₅, S₉

The switches between brackets may optionally be closed during thereferenced clock-phase.

In summary, the invention relates to a method and arrangement forcyclically AD converting an analog signal with a sampler capacitance andan integrator capacitance, comprising the steps of generating adifference signal multiplied by the ratio of said capacitances from theanalog signal and a reference signal, deriving a digital bit from saiddifference signal, doubling the difference signal multiplied by saidratio, shifting said doubled signal by the reference signal multipliedby said ratio and using the shifted signal as difference signalmultiplied by said ratio for the next cycle.

1. A method for cyclically converting an analog input signal to adigital output signal with a sampler capacitance and an integratorcapacitance characterized by comprising the steps of generating adifference signal by multiplying the difference of the analog signal anda reference signal by the ratio of said capacitances, deriving at leastone digital bit from said difference signal, substantially doubling thedifference signal, shifting said doubled difference signal by thereference signal multiplied by said ratio and using the shifted signalas difference signal multiplied by said ratio for a next cycle.
 2. Amethod as claimed in claim 1 whereby the digital output signal is amulti-bit digital word generated by means of an operational amplifierhaving an opamp-output connected to a comparator, the sampler capacitorthe integrator capacitor and switch means arranged and controlled toperform the conversion, characterized by: generating the differencesignal during a first phase-group of one or more clock-phases at theopamp-output, deriving the at least one digital bit during a secondphase-group of one or more clock-phases for constituting the digitalword and delivering at said opamp-output said difference signalmultiplied by said capacitance ratio, substantially doubling thedifference signal by generating during a third phase-group of one ormore clock-phases at the opamp-output a doubled difference signal whichis substantially twice said analog difference signal multiplied by saidcapacitance-ratio, shifting said doubled difference signal by generatingduring a fourth phase-group of one or more clock-phases at theopamp-output a shifted analog signal which is the opamp-output signaldelivered by the previous phase-group shifted by a bit-dependentreference signal multiplied by said capacitance ratio, and using saidshifted signal as difference signal for the second phase-group of thenext cycle.
 3. A method as claimed in claim 2 characterized bytransferring during the second phase-group the charge of the integratorcapacitor into the sampler capacitor generating said at least one bitfor constituting the digital word from the voltage across the samplercapacitor and subsequently transferring the charge of the samplercapacitor back into the integrator capacitor.
 4. A method as claimed inclaim 2 characterized by an iterative calibration process comprising thesteps of charging the sampler capacitor with a calibration voltage oftransferring the charge of the sampler capacitor to the integratorcapacitor of comparing the voltage across the integrator capacitor withsaid calibration voltage and of adding trimming capacitance to thesampler capacitance if the result of said comparison is higher than 1and by adding trimming capacitance to the integrator capacitance whenthe result of the comparison is lower than
 1. 5. A method as claimed inclaim 2 characterized by the third phase-group comprising the steps ofstoring the opamp-output voltage in first and second storage capacitorsof connecting the first and second storage capacitors in series with theinput of the opamp and connecting the integrator capacitor to the outputof the opamp whereby the voltages of the first and second storagecapacitors are added in the integrator capacitor, and of subsequentlyconnecting the integrator capacitor between the inverting input and theoutput of the opamp.
 6. An arrangement for cyclically converting ananalog input signal to a digital output signal with a samplercapacitance and an integrator capacitance characterized by beingarranged for performing the steps of generating a difference signal bymultiplying the difference of the analog signal and a reference signalby the ratio of said capacitances, deriving at least one digital bitfrom said difference signal, substantially doubling the differencesignal, shifting said doubled difference signal by the reference signalmultiplied by said ratio and using the shifted signal as differencesignal multiplied by said ratio for a next cycle.